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W83194BR-703/W83194BG-703 STEPLESS CLOCK FOR SIS 741 CHIPSET
W83194BR-703/W83194BG-703 WINBOND CLOCK GENERATOR FOR SIS 741/964 CHIPSETS
Date:
Jan./23/2006
Revision: 0.8
W83194BR-703/W83194BG-703
W83194BR-703/W83194BG-703 Data Sheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 n.a. 2,3,5, 6~14, 16~19 4 5 6 7 8 9 10 2,3,6,8, 18 04/18/2004 01/23/2006 0.7 0.8 n.a. n.a. 11/12/2003 0.6 n.a. 09/03/2003 0.5 n.a.
All of the versions before 0.50 are for internal use. First published preliminary version. Delete some power manage pin, Add register, SRC fix 100MHz, Add AC/DC Correct IC version and default value Add lead free part W83194BG-703
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 3 PIN DESCRIPTION..................................................................................................................... 4 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. Crystal I/O.................................................................................................................................4 CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs ...............................................................4 Fixed Frequency Outputs.........................................................................................................5 I2C Control Interface ................................................................................................................5 Power Management Pins.........................................................................................................5 Power Pins................................................................................................................................6
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7 I2C CONTROL AND STATUS REGISTERS............................................................................... 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 Register 0: Frequency Select (Default = 20h) .........................................................................8 Register 1: CPU Control (1 = Enable, 0 = Stopped) (Default: ECh).......................................8 Register 2: PCI, ZCLK Control (1 = Enable, 0 = Stopped) (Default: FFh) .............................9 Register 3: PCI, AGP Control (1 = Enable, 0 = Stopped) (Default: FFh) ...............................9 Register 4: 48MHz, REF, SRC Control (1 = Enable, 0 = Stopped) (Default: FFh)................9 Register 5: Watchdog Control (Default: 04h) ........................................................................10 Register 6: Skew Control (Default: 25h) ................................................................................10 Register 7: Winbond Chip ID (Default: 77h) (Read only)......................................................11 Register 8: M/N (Default: 90h) ...............................................................................................11 Register 9: N (Default: BBh)...................................................................................................11 Register 10: N & N3 (Default: 3Bh)........................................................................................12 Register 11: Spread Spectrum Programming (Default: 0Eh) ...............................................12 Register 12: Divisor and Step-less Enable Control (Default: 89h) .......................................12 Register 13: M/N Control (Default: 0Ah)................................................................................13 Register 14: Spread Spectrum Control (Default: 10h) ..........................................................14 Register 15: Spread Spectrum type Control (Default: 2Ch) .................................................14 Register 16: Skew Control (Default: 24h)..............................................................................15 Register 17: Slew rate Control (Default: 00h)........................................................................15 Register 18: Slew rate Control (Default: 00h)........................................................................15 Register 19: Slew rate Control (Default: D2h) .......................................................................16 Register 20: SRC select Control (Default: 88h) ....................................................................16 Register 21: Fix Mode Control (Default: 00h)........................................................................17 -II-
W83194BR-703/W83194BG-703
8. ACCESS INTERFACE .............................................................................................................. 18 8.1 8.2 8.3 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 10. 11. 12. Block Write protocol ...............................................................................................................18 Block Read protocol ...............................................................................................................18 Byte Write protocol .................................................................................................................18 Byte Read protocol.................................................................................................................18 ABSOLUTE MAXIMUM RATINGS .......................................................................................19 General Operating Characteristics ........................................................................................19 Skew Group timing clock........................................................................................................19 CPU (Open Drain) Electrical Characteristics.........................................................................20 SRC 0.7V Electrical Characteristics ......................................................................................20 AGP, ZCLK Electrical Characteristics ...................................................................................20 PCI Electrical Characteristics.................................................................................................21 24M, 48M Electrical Characteristics ......................................................................................21 REF Electrical Characteristics ...............................................................................................21 IOAPIC Electrical Characteristics ..........................................................................................22
SPECIFICATIONS .................................................................................................................... 19
ORDERING INFORMATION..................................................................................................... 22 HOW TO READ THE TOP MARKING...................................................................................... 23 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 24
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
1. GENERAL DESCRIPTION
The W83194BR-703 is a Clock Synthesizer for SIS 741 chipset with 964 South Bridge. W83194BR703 provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and AGP clocks setting, support two ZCLK clock and one pair current mode differential SRC clock outputs; all clocks are externally selectable with smooth transitions. The W83194BR-703 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-703 also has watchdog timer to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-703 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * * * * * 1 3.3V open drain Differential pairs clock outputs for CPU 1 3.3V open drain singled-ended clock output for chipset host bus. 1 pair 3.3V current mode differential SRC clock. 2 3.3V ZCLK clock outputs 2 AGP clock outputs 8 PCI synchronous clocks 2 2.5V IOAPIC clock outputs 1 24_48Mhz clock output for super I/O. 1 12_48 MHz clock output for USB. 3 14.318MHz REF clock outputs. ZCLK/AGP/PCI clock out supports synchronous and asynchronous mode Smooth frequency switch with selections from 100 to 218MHz Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Programmable clock outputs Skew control
* 48-pin SSOP package
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
3. PIN CONFIGURATION
#: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
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W83194BR-703/W83194BG-703
4. BLOCK DIAGRAM
PLL2
Divider
12_48MHz 24_48MHz^ 3
XIN XOUT
XTAL OSC
REF 0:2
2
PLL1 Spread Spectrum
CPUT0:1 CPUC0 SRCT SRCC
VCOCLK
2
ZCLK0:1
M/N/Ratio ROM
2
Divider
2
IOAPIC0:1 AGP 0:1
FS(0:3) SEL12_48MHz#& SEL24_48MHz#& Latch &POR
8
PCI_F0:1, PCI_0:5
Control Logic &Config Register IREF Rref
SDATA* SCLK*
I2C Interface
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT OD # * &
Input Latched input at power up, internal 120k pull up. Latched input at power up, internal 120k pull down. Output Open Drain Active Low Internal 120k pull-up Internal 120 k pull-down
5.1
Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
6 7
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF).
5.2
CPU, AGP, ZCLK and PCI, IOAPIC Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
38,37 40 43,42 31,30 9,10 14
CPUT0 CPUC0 CPUT1 SRCT, SRCC AGP_0: 1 ZCLK0: 1 PCI_F0 FS2* PCI_F1 FS3*
OD OD OUT OUT OUT OUT INtp120k OUT INtp120k OUT OUT
3.3V open drain differential clock outputs for AMD K7 CPU 3.3V open drain singled -ended synchronize with CPUT0, For chipset host bus Current mode differential clock outputs for SRC 3.3V AGP clock outputs. 3.3V ZCLK clock outputs, For MuTIOL bus. 3.3V PCI free running clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. 3.3V PCI free running clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency, This is internal 120K pull up. Low skew (< 250ps) PCI clock outputs. 2.5V IOAPIC outputs.
15
16,17,20,21 PCI [0:5] ,22,23 47,46 IOAPIC [0:1]
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W83194BR-703/W83194BG-703
5.3 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
REF0 2 FS0& REF1 3 4 27 FS1& REF2 12_48MHz SEL12_48MHz# * 24_48MHz 26 SEL24_48#&
OUT INtd120k OUT INtd120k OUT OUT INtp120k OUT INtd120k
14.318MHz output. Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 14.318MHz output. Latched input for FS1 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 14.318MHz output. 12 MHz (default) or 48MHz clock output. Latched input at initial power up for 12_48MHz output type selecting, SEL12_48MHz= 0 is 48 MHz, SEL12_48MHz=1 is 12MHZ; This is internal 120K pull up. 24MHz or 48MHz (default) clock output. Latched input at initial power up for 24_48MHz output type selecting, SEL24_48MHz= 0 is 48 MHz, SEL24_48MHz=1 is 24MHZ; This is internal 120K pull down.
5.4
I2C Control Interface
PIN PIN NAME TYPE
2
DESCRIPTION
33 12
SDATA* SCLK*
I/OD IN
Serial data of I C 2-wire control interface with internal pullup resistor. Serial clock of I2C 2-wire control interface with internal pullup resistor.
5.5
Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
Deciding the reference current for the SRCT/C pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. The table is show as follows. MULTSEL Board Target Reference R, Output Ioh @ (PIN 11) Trace/ Term Iref=VDD/(3*Rr Current Z Z ) 1 0 50 Ohms 50 Ohms R=475 1% Iref=2.32mA R=221 1% Iref=5mA Ioh= 6*Iref Ioh= 4*Iref 0.7V @ 50 1.0V @ 50
34
IREF
OUT
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
5.6 Power Pins
PIN PIN NAME TYPE DESCRIPTION
1 13,19 29 44 28 11 48 36 5,8,18,24,25,32, 35,39,41,45
VDDREF VDDPCI VDDAGP VDDSRC VDD48 VDDZ VDDI VDDA GND
PWR PWR PWR PWR PWR PWR PWR PWR PWR
3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for AGP. 2.5V power supply for SRC. 3.3V power supply for 48MHz. 3.3V power supply for ZCLK. 2.5V power supply for IOAPIC 3.3V power supply for Analog core logic. Ground pin
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W83194BR-703/W83194BG-703
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3). FS4 FS3 FS2 FS1 FS0 CPU (MHZ) SRC (MHZ) ZCLK (MHZ) AGP (MHZ) PCI (MHZ) 0 0 0 0 0 200.00 100.00 133.33 66.67 33.33 0 0 0 0 1 200.00 100.00 133.33 66.67 33.33 0 0 0 1 0 200.99 100.00 133.99 67.00 33.50 0 0 0 1 1 190.00 100.00 126.67 63.33 31.67 0 0 1 0 0 100.00 100.00 133.33 66.67 33.33 0 0 1 0 1 100.00 100.00 133.33 66.67 33.33 0 0 1 1 0 100.99 100.00 134.65 67.33 33.66 0 0 1 1 1 95.00 100.00 126.67 63.33 31.67 0 1 0 0 0 160.00 100.00 133.33 66.67 33.33 0 1 0 0 1 166.66 100.00 138.88 69.44 34.72 0 1 0 1 0 161.58 100.00 134.65 67.33 33.66 0 1 0 1 1 152.00 100.00 126.67 63.33 31.67 0 1 1 0 0 133.33 100.00 133.33 66.67 33.33 0 1 1 0 1 133.33 100.00 133.33 66.67 33.33 0 1 1 1 0 133.99 100.00 133.99 67.00 33.50 0 1 1 1 1 126.66 100.00 126.66 63.33 31.67 1 0 0 0 0 206.00 100.00 137.33 68.67 34.33 1 0 0 0 1 210.00 100.00 140.00 70.00 35.00 1 0 0 1 0 214.00 100.00 142.67 71.33 35.67 1 0 0 1 1 218.00 100.00 145.33 72.67 36.33 1 0 1 0 0 103.00 100.00 137.33 68.67 34.33 1 0 1 0 1 105.00 100.00 140.00 70.00 35.00 1 0 1 1 0 107.00 100.00 142.67 71.33 35.67 1 0 1 1 1 109.00 100.00 145.33 72.67 36.33 1 1 0 0 0 164.80 100.00 137.33 68.67 34.33 1 1 0 0 1 168.00 100.00 140.00 70.00 35.00 1 1 0 1 0 171.20 100.00 142.67 71.33 35.67 1 1 0 1 1 174.40 100.00 145.33 72.67 36.33 1 1 1 0 0 137.33 100.00 137.33 68.67 34.33 1 1 1 0 1 140.00 100.00 140.00 70.00 35.00 1 1 1 1 0 142.67 100.00 142.67 71.34 35.67 1 1 1 1 1 145.33 100.00 145.33 72.67 36.33
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
7. I2C CONTROL AND STATUS REGISTERS
7.1
BIT
Register 0: Frequency Select (Default = 20h)
NAME PWD DESCRIPTION
7 6 5 4 3 2
SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL
0 0 1 0 0 0 Enable software table selection FS [4:0]. 0 = Hardware table setting (Jump mode). 1 = Software table setting through Bit7~3. (Jump less mode) Enable spread spectrum mode under clock output. 0 = Spread Spectrum mode disable 1 = Spread Spectrum mode enable After watchdog timeout 0 = Reload the hardware FS [4:0] latched pins setting. 1 = Reload the desirable frequency table selection defined at Reg-5 Bit 4~0. Frequency selection by software via I2C
1
EN_SPSP
0
0
EN_SAFE_FREQ
0
7.2
BIT
Register 1: CPU Control (1 = Enable, 0 = Stopped) (Default: ECh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved 40 38,37 Reserved 15 14 3 2
1 1 1 X X X X X
Reserved CPUT1 output control CPUT0 / C0 output control Reserved. Default: 0 (Read only) Power on latched value of FS3 pin. Default: 1 (Read only) Power on latched value of FS2 pin. Default: 1 (Read only) Power on latched value of FS1 pin. Default: 0 (Read only) Power on latched value of FS0 pin. Default: 0 (Read only)
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W83194BR-703/W83194BG-703
7.3
BIT
Register 2: PCI, ZCLK Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
15 14 10 9 23 22 21
1 1 1 1 1 1 1 1
Reserved PCI_F1 output control PCI_F0 output control ZCLK1 output control ZCLK0 output control PCI5 output control PCI4 output control PCI3 output control
7.4
BIT
Register 3: PCI, AGP Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
20 17 16 SEL12_48 47 46 30 31
1 1 1 X 1 1 1 1
PCI2 output control PCI1 output control PCI0 output control 12 _ 48 MHz output selection, 1: 12 MHz (default) 0: 48 MHz. Default value follow hardware trapping data on SEL12_48# pin. IOAPIC1 output control IOAPIC0 output control AGP_1 output control AGP_0 output control
7.5
BIT
Register 4: 48MHz, REF, SRC Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
26 27 4 3 2 47,46 -
1 1 1 1 1 1 1 1
24_48MHz output control 12_48MHz output control Reserved REF2 output control REF1 output control REF0 output control SRC output control Reserved
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
7.6
BIT
Register 5: Watchdog Control (Default: 04h)
NAME PWD DESCRIPTION
7
SEL24_48
X
24 / 48 MHz output selection, 1: 24 MHz 0: 48 MHz (Default), Default value follow hardware trapping data on SEL24_48# pin. Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. Read Back only. Timeout Flag. This bit is Read Only.
6
CNT_EN
0
5 4 3 2 1 0
WD_TIMEOUT SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 1 0 0
1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting.
These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1.
7.7
BIT
Register 6: Skew Control (Default: 25h)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved CSKEW<2> CSKEW<1> CSKEW<0>
0 0 1 0 0 1 0 1
Reserved Reserved Reserved CPU1 to CPU0 skew control Skew resolution is 250ps The decision of skew direction is same as CSKEW<2:0> setting
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W83194BR-703/W83194BG-703
7.8
BIT
Register 7: Winbond Chip ID (Default: 77h) (Read only)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0 1 1 1 0 1 1 1
Winbond Chip ID. W83194BR-703 (SA5877). Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
7.9
BIT
Register 8: M/N (Default: 90h)
NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
NVAL<8> MVAL<6> MVAL<5> MVAL<4> MVAL<3> MVAL<2> MVAL<1> MVAL<0>
X X X X X X X X
Programmable N divisor value. Bit 7 ~0 are defined in the Register 9.
Programmable M divisor
7.10 Register 9: N (Default: BBh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
NVAL<7> NVAL<6> NVAL<5> NVAL<4> NVAL<3> NVAL<2> NVAL<1> NVAL<0>
X X X X X X X X Programmable N divisor bit 7 ~0. The bit 8 is defined in Register 8, The bit 9 is defined in Register 10
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
7.11 Register 10: N & N3 (Default: 3Bh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
NVAL<9> N3VAL<6> N3VAL<5> N3VAL<4> N3VAL<3> N3VAL<2> N3VAL<1> N3VAL<0>
X X X X X X X X
Programmable N divisor bit 9.
Programmable N3 divisor bit 6 ~0 for programmable SRC clock. PS: Frequency range: 86.8M ~ 115.2M Resolution: 224K
7.12 Register 11: Spread Spectrum Programming (Default: 0Eh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 0 1 1 1 0 Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0.
7.13 Register 12: Divisor and Step-less Enable Control (Default: 89h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
M_NACC_EN KVAL<9> KVAL<5> Reserved Reserved KVAL<2> KVAL<1> KVAL<0>
1 X X X X X X X
Enable variable accumulation period for M divisor 1: Enable, 0: Disable (Original timing) Define the ZCLK divider ratio Table-2 integrate the all divider configuration Reserved Define the CPU divider ratio Refer to Table-2
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W83194BR-703/W83194BG-703
Table-2 CPU, ZCLK divider ratio selection Table
LSB MSB ZCLK BIT5 CPU BIT1, 0
0 Div3 Div5
1 Div4 Div6
00 Div2 Div6
01 Div3 Div8
10 Div4 Div8
11 Div5 Div8
Bit2/ Bit4/ Bit9
0 1
7.14 Register 13: M/N Control (Default: 0Ah)
BIT NAME PWD DESCRIPTION
7
EN_MN_PROG
0
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<4:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 7). Programmable N divisor bit 10. Variable accumulation period for M divisor. Depend On VCO Frequency. 00: 400M 10: 667M 01: 533M 11: 800M
6 5 4 3 2 1 0
NVAL<10> DIVM_P1 DIVM_P0 IVAL<3> IVAL<2> IVAL<1> IVAL<0>
X 0 0 X X X X
Charge pump current selection
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
7.15 Register 14: Spread Spectrum Control (Default: 10h)
BIT NAME PWD DESCRIPTION
7
CPUT_DRI
0
6
SRCT_DRI
0
CPUT output state in during POWER DOWN or Stop mode assertion. 1: Driven (2*Iref) 0: Tristate (Floating) CPUC always tri-state (floating) in power down Assertion. SRC_T output state in during POWER DOWN or Stop mode assertion. 1: Driven (6*Iref => STOP mode) (2*Iref => POWER DOWN) 0: Tristate (Floating) SRC_C always tri-state (floating) in power down Assertion.
5 4 3 2 1 0
SPCNT<5> SPCNT<4> SPCNT<3> SPCNT<2> SPCNT<1> SPCNT<0>
0 1 0 0 0 0
Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us
7.16 Register 15: Spread Spectrum type Control (Default: 2Ch)
BIT NAME PWD DESCRIPTION
7 6 5 4
INV_CPU INV_ZCLK Reserved SPSP1
0 0 1 0
Invert the CPU phase, 0: Default, 1: Inverse Invert the ZCLK phase, 0: Default, 1: Inverse Reserved Spread Spectrum type select. 00: Down 1% 0.5% 01: Down
3
SPSP0
1
10: Center +/- 0.5% 11: Center +/- 0.25% CPU1 to AGP skew control. Skew resolution is 250ps The decision of skew direction is same as ASKEW<2:0> setting
2 1 0
ASKEW<2> ASKEW<1> ASKEW<0>
1 0 0
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W83194BR-703/W83194BG-703
7.17 Register 16: Skew Control (Default: 24h)
Bit
Name INV_AGP INV_PCI ZSKEW<2> ZSKEW<1> ZSKEW<0> PSKEW<2> PSKEW<1> PSKEW<0>
PWD Description 0 0 1 0 0 1 0 0 Invert the AGP phase, 0: Default, 1: Inverse Invert the PCI phase, 0: Default, 1: Inverse CPU1 to ZCLK skew control Skew resolution is 250ps The decision of skew direction is same as ZSKEW<2:0> setting CPU1 to PCI skew control Skew resolution is 250ps The decision of skew direction is same as PSKEW<2:0> setting
7 6 5 4 3 2 1 0
7.18 Register 17: Slew rate Control (Default: 00h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved INV_USB12 PCI_F0_S2 PCI_F0_S1 IOAPIC_S2 IOAPIC_S1 AGP_10_S2 AGP_10_S1
0 0 0 0 0 0 0 0
Reserved Invert the USB12_48 phase, 0: In phase with USB24_48 1: 180 degrees out of phase PCI_F1 / PCI_F0 slew rate control 11: Strong, 00: Weak, 10/01: Normal IOAPIC1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal AGP_1 / AGP_0 slew rate control 11: Strong, 00: Weak, 10/01: Normal
7.19 Register 18: Slew rate Control (Default: 00h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI_5_S2 PCI_5_S1 PCI_42_S2 PCI_42_S1 PCI_10_S2 PCI_10_S1 REF_S2 REF_S1
0 0 0 0 0 0 0 0
PCI5 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI4, 3,2 slew rate control 11: Strong, 00: Weak, 10/01: Normal PCI1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal REF0, 1, 2 slew rate control 11: Strong, 00: Weak, 10/01: Normal
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
7.20 Register 19: Slew rate Control (Default: D2h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU1S_EN CPU0S_EN ZCLK_S2 ZCLK_S1 INV_USB48 USB48_S2 USB48_S1 Reserved
1 1 0 1 0 0 1 0
Stop CPU1 clocks, 1: Enable stop feature, 0: Disable Stop CPU0 clocks, 1: Enable stop feature, 0: Disable ZCLK1, 0 slew rate control 11: Strong, 00: Weak, 10/01: Normal Invert the USB48 phase 0: In phase with USB24_48 1: 180 degrees out of phase USB48/USB12_48/USB24_48 slew rate control 11: Strong, 00: Weak, 10/01: Normal Reserved
7.21 Register 20: SRC select Control (Default: 88h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
Reserved SEC<6> SEC<5> SEC<4> SEC<3> SEC<2> SEC<1> SEC<0>
1 0 0 0 1 0 0 0
Reserved for test only please don't modify it.
Setting the down count depth. One bit resolution Represent 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value.
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W83194BR-703/W83194BG-703
7.22
BIT
Register 21: Fix Mode Control (Default: 00h)
NAME PWD DESCRIPTION
7
TRI-EN
0
Tri-state all output if set 1 ZCLK output frequency select mode (Only valid under FIX_ADDR<2:0> is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table PCI output frequency select mode (Only valid under FIX_ADDR<2:0> is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table AGP output frequency select mode (Only valid under FIX_ADDR<2:0> is nonzero) 0: Output frequency according to frequency selection table 1: Output frequency according to FIX frequency table Reserved for test only please don't modify it. Asynchronous ZCLK/AGP/PCI frequency table selection FIX_ADDR<2:0> 001: 132 / 66 / 33M 010:132 / 75.43 / 37.7M 100:176 / 88 / 44M 110:132 / 75.43 / 33M 000: Clock from PLL1 011: 132 / 88 / 44M 101: 132 / 66 / 33M 111: 132 / 88 / 33M
6
FIX_ZCLK
0
5
FIX_PCI
0
4
FIX_AGP
0
3 2 1
Reserved FIX_ADDR<2> FIX_ADDR<1>
0 0 0
0
FIX_ADDR<0>
0
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
8. ACCESS INTERFACE
The W83194BR-703 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-703 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8'h00
8.3
Byte Write protocol
8.4
Byte Read protocol
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W83194BR-703/W83194BG-703
9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model)
-0.5V to +4.6V - 0.5 V to + 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2
General Operating Characteristics
PARAMETER SYMBOL MIN MAX UNITS TEST CONDITIONS
VDD48=VDDAGP=VDDREF=VDDPCI= 3.3V 5 %, TA = 0C to +70C, Cl=10pF Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance VIL VIH VOL VOH Idd Cin Cout Lin 0.8 2.0 0.4 2.4 350 5 6 7 Vdc Vdc Vdc Vdc mA pF pF nH
All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 Mhz with load
9.3
Skew Group timing clock
PARAMETER MIN TYP MAX UNITS TEST CONDITIONS
VDD48=VDDAGP=VDDREF=VDDPCI = 3.3V 5 %, TA = 0C to +70C, Cl=10pF AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew 1.5 2.6 3.5 200 250 500 1000 500 ns ps ps ps ps ps Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
9.4 CPU (Open Drain) Electrical Characteristics
Parameter Rise Time Fall Time Absolute Voltages Duty Cycle crossing point Min 550 Max 900 900 1250 250 45 55 Units ps ps mV ps % Test Conditions 100 to 200 Mhz, Vol=20%, Voh=80% 100 to 200Mhz, Vol=20%, Voh=80% 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz
TA = 0C to +70C, external 1.5V pull-up
Cycle to Cycle jitter
9.5
SRC 0.7V Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDSRC= 3.3V 5 %, TA = 0C to +70C, 100 Mhz , Measure from Vol=0.175 to Voh=0.525 100 Mhz, Measure from Vol=0.175 to Voh=0.525 100 Mhz 100 Mhz, Measure from differential wavefrom 100 Mhz, Measure from differential wavefrom
Rise Time Fall Time Absolute Voltages crossing point
175 175 250
700 700 550 125
ps ps mV ps %
Cycle to Cycle jitter Duty Cycle 45
55
9.6
AGP, ZCLK Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
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W83194BR-703/W83194BG-703
9.7 PCI Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDPCI= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 250 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
9.8
24M, 48M Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 500 500 2000 2000 500 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
9.9
REF Electrical Characteristics
PARAMETER MIN MAX UNITS TEST CONDITIONS
VDDREF= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 1000 1000 4000 4000 1000 55 ps ps ps % mA mA mA mA Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
9.10 IOAPIC Electrical Characteristics
VDDI= 2.5V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER MIN MAX UNITS TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
400 400 45 -27
1600 1600 500 55 -27
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.0V Measure from 2.0V to 0.4V Measure 1.25V point Vout=1.0V Vout=2.375V Vout=1.2V Vout=0.3V
27 30
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194BR-703 W83194BG-703
48 PIN SSOP 48 PIN SSOP (Lead free package)
Commercial, 0C to +70C Commercial, 0C to +70C
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W83194BR-703/W83194BG-703
11. HOW TO READ THE TOP MARKING
W83194BR-703 28051234 442GAASA
1st line: Winbond logo and the type number:
W83194BG-703 28051234 342GAASA
Normal part :W83194BR-703, Lead free part: W83194BG-703 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G A A SA 442: packages made in '2004, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Jan. 2006 Revision 0.8
W83194BR-703/W83194BG-703
12. PACKAGE DRAWING AND DIMENSIONS
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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